Design of a Replica Circuit with Body-Bias Tunability for Variation Tracking and Compensation in CMOS 28nm FD-SOI
Type: Master project for one student or semester project for two students
- Investigation of the standard-cell library across variations
- Design of a replica circuit with programmable delay line and time-to-digital converter
- Performance analysis of the replica delay tracking
- Analysis of delay compensation through body-bias in CMOS 28nm FD-SOI
Design of a synthesizeable digital frequency locked loop (FLL)
Semester Project for 2 OR Master Project
Description: Modern system on chips designs integrate multiple IP blocks to implement all kinds of functionality. Each of these blocks may have been designed for a different nominal clock frequency which has to be supplied. An FLL can be used to derive a fast internal clock from a single slow but precise reference clock generated by an external crystal circuit.
The goal of this project is to implement a programmable FLL, capable of generating custom frequencies over a wide range, utilizing body biasing as a knob to fine tune the integrated oscillating circuit. The final circuit operation is to be verified across process corners and supply voltages.
Prerequisites: Knowledge of VHDL, Basic knowledge of analog simulation of digital cells (ideally Cadence Virtuoso)
Workload: 50% VHDL, 30% Digital cell design, 20% Simulation & Verification
Area: IC Design, Digital design, Mixed Signal, Clock domain crossing
Supervisor: Christoph Müller
Date added: 30-11-2016