All TCL Publications

2019

Conference Papers

M. van Beirendonck; L.-C. Trudeau; P. Giard; A. Balatsoukas-Stimming : A Lyra2 FPGA Core for Lyra2REv2-Based Cryptocurrencies. 2019-01-01. IEEE International Symposium on Circuits and Systems (IEEE ISCAS), Sapporo, JAPAN, May 26-29, 2019.
E. V. Bravo; A. Bonetti; A. Burg : Data-Retention-Time Characterization of Gain-Cell eDRAMs across the Design and Variations Space. 2019-01-01. IEEE International Symposium on Circuits and Systems (IEEE ISCAS), Sapporo, JAPAN, May 26-29, 2019.
E. Testa; L. Amaru; M. Soeken; A. Mishchenko; P. Vuillod et al. : Scalable Boolean Methods in a Modem Synthesis Flow. 2019-01-01. Design, Automation & Test in Europe Conference & Exhibition (DATE), Florence, ITALY, Mar 25-29, 2019. p. 1643-1648.

Theses

A. Bonetti / A. P. Burg; A. S. Teman (Dir.) : Low-Power Design of Digital VLSI Circuits around the Point of First Failure. Lausanne, EPFL, 2019. DOI : 10.5075/epfl-thesis-9180.

2018

Journal Articles

H. Yueksel; M. Braendli; A. Burg; G. Cherubini; R. D. Cideciyan et al. : Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders; Ieee Transactions On Circuits And Systems I-Regular Papers. 2018-10-01. DOI : 10.1109/TCSI.2018.2803735.
A. Balatsoukas-Stimming; A. P. Liavas : Design of LDPC Codes for the Unequal Power Two-User Gaussian Multiple Access Channel; Ieee Wireless Communications Letters. 2018-10-01. DOI : 10.1109/LWC.2018.2833855.
A. Balatsoukas-Stimming; A. Burg : Faulty Successive Cancellation Decoding of Polar Codes for the Binary Erasure Channel; IEEE TRANSACTIONS ON COMMUNICATIONS. 2018. DOI : 10.1109/TCOMM.2017.2771243.
R. Giterman; A. Fish; N. Geuli; E. Mentovich; A. Burg et al. : An 800-MHz Mixed-V-T 4T IFGC Embedded DRAM in 28-nm CMOS Bulk Process for Approximate Storage Applications; IEEE JOURNAL OF SOLID-STATE CIRCUITS. 2018. DOI : 10.1109/JSSC.2018.2820145.
C. Condo; P. Giard; F. Leduc-Primeau; G. Sarkis; W. Gross : A 9.52 dB NCG FEC Scheme and 162 b/Cycle Low-Complexity Product Decoder Architecture; IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS. 2018. DOI : 10.1109/TCSI.2017.2745902.
R. Ghanaatian; A. Balatsoukas-Stimming; T. Muller; M. Meidlinger; G. Matz et al. : A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message Passing; IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 2018. DOI : 10.1109/TVLSI.2017.2766925.
R. Giterman; A. Fish; A. Burg; A. Teman : A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI; IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS. 2018. DOI : 10.1109/TCSI.2017.2747087.
A. Burg; A. Chattopadhyay; K.-Y. Lam : Wireless Communication and Security Issues for Cyber-Physical Systems and the Internet-of-Things; Proceedings Of The IEEE. 2018. DOI : 10.1109/Jproc.2017.2780172.
P. Giard; A. K. Balatsoukas Stimming; G. Sarkis; C. Thibeault; W. J. Gross : Fast Low-Complexity Decoders for Low-Rate Polar Codes; Journal of Signal Processing Systems. 2018. DOI : 10.1007/s11265-016-1173-y.

Conference Papers

A. Balatsoukas-Stimming : Non-Linear Digital Self-Interference Cancellation for In-Band Full-Duplex Radios Using Neural Networks. 2018-01-01. IEEE 19th International Workshop on Signal Processing Advances in Wireless Communications (SPAWC), Kalamata, GREECE, Jun 25-28, 2018. p. 1-5.
P. Giard; A. Burg : Fast-SSC-Flip Decoding of Polar Codes. 2018. DOI : 10.1109/WCNCW.2018.8369026.
A. Bonetti; J. Constantin; A. S. Teman; A. P. Burg : A Timing-Monitoring Sequential for Forward and Backward Error-Detection in 28 nm FD-SOI. 2018. IEEE International Symposium on Circuits and Systems (ISCAS), Florence, ITALY, May 27-30, 2018.

2017

Journal Articles

D. Rossi; A. Pullini; I. Loi; M. Gautschi; F. K. Gurkaynak et al. : Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster; Ieee Micro. 2017. DOI : 10.1109/MM.2017.3711645.
P. Giard; A. K. Balatsoukas Stimming; T. C. Müller; A. Bonetti; C. Thibeault et al. : PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes; IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 2017. DOI : 10.1109/JETCAS.2017.2745704.
A. Bonetti; A. S. Teman; P. Flatresse; A. P. Burg : Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters; IEEE Transactions on Circuits and Systems I: Regular Papers. 2017. DOI : 10.1109/TCSI.2017.2698138.
A. Bonetti; N. A. Preyss; A. S. Teman; A. P. Burg : Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes; ACM Transactions on Design Automation of Electronic Systems. 2017. DOI : 10.1145/3054744.
J. Constantin; R. Houlmann; N. Preyss; N. Walenta; H. Zbinden et al. : An FPGA-Based 4 Mbps Secret Key Distillation Engine for Quantum Key Distribution Systems; Journal Of Signal Processing Systems For Signal Image And Video Technology. 2017. DOI : 10.1007/s11265-015-1086-1.

Conference Papers

P. Giard; A. K. Balatsoukas Stimming; A. P. Burg : Blind detection of polar codes. 2017. IEEE International Workshop on Signal Processing Systems (SiPS), Lorient, France, October 3-5, 2017. DOI : 10.1109/SiPS.2017.8109977.
A. K. Balatsoukas Stimming; P. Giard; A. P. Burg : Comparison of Polar Decoders with Existing Low-Density Parity-Check and Turbo Decoders. 2017. IEEE Wireless Communications and Networking Conference (WCNC), San Francisco, CA, USA, Mar. 2017. p. 1-6. DOI : 10.1109/WCNCW.2017.7919106.

Theses

H. Yüksel / A. P. Burg; T. Toifl (Dir.) : High-Speed Wireline Link Design. Lausanne, EPFL, 2017. DOI : 10.5075/epfl-thesis-7758.

Talks

N. A. Preyss; P. Giard; A. K. Balatsoukas Stimming; A. P. Burg : Polar codes and APSK modulation - Just good friends ; Information Theory and Applications Workshop (ITA), San Diego, CA, USA, Feb. 12-17, 2017.

2016

Journal Articles

M. Yousefbeiki; A. C. M. Austin; J. R. Mosig; A. Burg; J. Perruisseau-Carrier : Spatial Multiplexing of QPSK Signals With a Single Radio: Antenna Design and Over-the-Air Experiments; Ieee Transactions On Antennas And Propagation. 2016. DOI : 10.1109/Tap.2016.2624138.
A. Teman; D. Rossi; P. Meinerzhagen; L. Benini; A. Burg : Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement; Acm Transactions On Design Automation Of Electronic Systems. 2016. DOI : 10.1145/2890498.
L. Moyal; I. Levi; A. Teman; A. Fish : Synthesis of Dual Mode Logic; Integration-The Vlsi Journal. 2016. DOI : 10.1016/j.vlsi.2016.07.004.
A. C. M. Austin : Wireless Channel Characterization in Burning Buildings Over 100-1000 MHz; Ieee Transactions On Antennas And Propagation. 2016. DOI : 10.1109/Tap.2016.2562671.
L. Atias; A. Teman; R. Giterman; P. Meinerzhagen; A. Fish : A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications; Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 2016. DOI : 10.1109/Tvlsi.2016.2518220.
C. Senning; G. Karakonstantis; A. Burg : Cross-Layer Energy-Efficiency Optimization of Packet Based Wireless MIMO Communication Systems; Journal Of Signal Processing Systems For Signal Image And Video Technology. 2016. DOI : 10.1007/s11265-015-1003-7.
O. Andersson; B. Mohammadi; P. Meinerzhagen; A. Burg; J. N. Rodrigues : Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS; Ieee Transactions On Circuits And Systems I-Regular Papers. 2016. DOI : 10.1109/Tcsi.2016.2537931.
N. Edri; P. Meinerzhagen; A. Teman; A. Burg; A. Fish : Silicon-Proven, Per-Cell Retention Time Distribution Model for Gain-Cell Based eDRAMs; Ieee Transactions On Circuits And Systems I-Regular Papers. 2016. DOI : 10.1109/Tcsi.2015.2512706.
S. Brenna; A. Bonetti; A. Bonfanti; A. Lacaita : An Efficient Tool for the Assisted Design of SAR ADCs Capacitive DACs; Integration, the VLSI Journal (Elsevier). 2016. DOI : 10.1016/j.vlsi.2015.12.005.
R. Giterman; A. Teman; P. Meinerzhagen; L. Atias; A. Burg et al. : Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications; Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 2016. DOI : 10.1109/TVLSI.2015.2394459.

Conference Papers

P. Giard; A. K. Balatsoukas Stimming; T. C. Müller; A. P. Burg; C. Thibeault et al. : A Multi-Gbps Unrolled Hardware List Decoder Systematic Polar Code. 2016. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, Nov. 2016. p. 1194-1198. DOI : 10.1109/ACSSC.2016.7869561.
H. Yueksel; G. Cherubini; R. D. Cideciyan; S. Furrer; A. Burg et al. : High-Speed Link With Trellis-Coded Modulation and Reed Solomon Coding. 2016. IEEE Conference on Standards for Communications and Networking (CSCN), Berlin, GERMANY, OCT 31-NOV 02, 2016.
P. Giard; G. Sarkis; A. Balatsoukas-Stinning; Y. Fan; C.-Y. Tsui et al. : Hardware Decoders for Polar Codes: An Overview. 2016. IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, CANADA, MAY 22-25, 2016. p. 149-152.
J. Constantin; A. Burg; Z. Wang; A. Chattopadhyay; G. Karakonstantis : Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance. 2016. 53rd ACM/EDAC/IEEE Design Automation Conference (DAC), Austin, TX, JUN 05-09, 2016. DOI : 10.1145/2897937.2696095.
H. Yueksel; M. Braendli; A. Burg; G. Cherubini; R. D. Cideciyan et al. : A 4.1 pJ/b 25.6 Gb/s 4-PAM Reduced-State Sliding-Block Viterbi Detector in 14 nm CMOS. 2016. 46th European Solid-State Device Research Conference (ESSDERC) / 42nd European Solid-State Circuits Conference (ESSCIRC), Lausanne, SWITZERLAND, SEP 12-15, 2016. p. 309-312.
A. P. Burg : Approximate Computing for Unreliable Silicon. 2016. 11th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).
S. A. Hashemi; A. Balatsoukas-Stimming; P. Giard; C. Thibeault; W. J. Gross : Partitioned Successive-Cancellation List Decoding Of Polar Codes. 2016. IEEE International Conference on Acoustics, Speech, and Signal Processing, Shanghai, PEOPLES R CHINA, MAR 20-25, 2016. p. 957-960.
R. Giterman; A. Teman; P. Meinerzhagen; A. Fish; A. Burg : A Process Compensated Gain Cell Embedded-DRAM for Ultra-Low-Power Variation-Aware Design. 2016. IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, CANADA, MAY 22-25, 2016. p. 1006-1009.
R. Ghanaatian Jahromi; P. Whatmough; J. H.-F. Constantin; A. S. Teman; A. P. Burg : A Low-Power Correlator for Wakeup Receivers with Algorithm Pruning through Early Termination. 2016. 2016 IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, Canada, May 22-25, 2016. p. 2667-2670.
D. Rossi; A. Pullini; I. Loi; M. Gautschi; F. K. Gürkaynak et al. : 193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing. 2016. 2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX), Yokohama, Japan, April 20-22, 2016. DOI : 10.1109/CoolChips.2016.7503670.
A. Austin; A. K. Balatsoukas Stimming; A. Burg : Digital Predistortion of Power Amplifier Non-Linearities for Full-Duplex Transceivers. 2016. 17th IEEE International workshop on Signal Processing Advances in Wireless Communications, Edinburgh, Scotland, UK, July 3-6, 2016.
J. H.-F. Constantin; A. Bonetti; A. S. Teman; T. C. Müller; L. F. Schmid et al. : DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment. 2016. 42nd European Solid-State Circuits Conference (ESSCIRC), Lausanne, Switzerland, September 12-15, 2016. p. 261-264.
O. Afisiadis; A. C. M. Austin; A. K. Balatsoukas Stimming; A. Burg : Sliding Window Spectrum Sensing for Full-Duplex Cognitive Radios with Low Access-Latency. 2016. IEEE 83rd Vehicular Technology Conference, Nanjing, China, 15-18 May.
J. H.-F. Constantin; Z. Wang; G. Karakonstantis; A. Chattopadhyay; A. P. Burg : Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance. 2016. 53rd ACM/EDAC/IEEE Design Automation Conference (DAC), Austin, Texas, USA, June 5-9, 2016. p. 13:1-13:6. DOI : 10.1145/2897937.2898095.
L. G. Duch; P. Garcia del Valle; S. Ganapathy; A. P. Burg; D. Atienza Alonso : Energy vs. Reliability Trade-offs Exploration in Biomedical Ultra-Low Power Devices. 2016. Design, Automation and Test in Europe Conference (DATE '16), Dresden, Germany, March 14-18, 2016. p. 838-841.

Theses

J. H.-F. Constantin / A. P. Burg; D. Atienza Alonso (Dir.) : Microarchitectural Low-Power Design Techniques for Embedded Microprocessors. Lausanne, EPFL, 2016. DOI : 10.5075/epfl-thesis-7168.
A. K. Balatsoukas Stimming / A. P. Burg (Dir.) : Hardware implementation aspects of polar decoders and ultra high-speed LDPC decoders. Lausanne, EPFL, 2016. DOI : 10.5075/epfl-thesis-7297.
N. A. Preyss / A. P. Burg (Dir.) : Modulation, Coding, and Receiver Design for Gigabit mmWave Communication. Lausanne, EPFL, 2016. DOI : 10.5075/epfl-thesis-7111.

2015

Journal Articles

A. Austin : Performance estimation for indoor wireless systems using FDTD method; Electronics Letters. 2015. DOI : 10.1049/el.2015.1093.
H. Kroell; S. Zwicky; B. Weber; C. Roth; D. Tschopp et al. : An Evolved GSM/EDGE Baseband ASIC Supporting Rx Diversity; Ieee Journal Of Solid-State Circuits. 2015. DOI : 10.1109/Jssc.2015.2417802.
A. Balatsoukas-Stimming; M. B. Parizi; A. Burg : LLR-Based Successive Cancellation List Decoding of Polar Codes; Ieee Transactions On Signal Processing. 2015. DOI : 10.1109/Tsp.2015.2439211.
A. Balatsoukas-Stimming; A. Austin; P. Belanovic; A. Burg : Baseband and RF hardware impairments in full-duplex wireless systems: experimental characterisation and suppression; EURASIP Journal on Wireless Communications and Networking. 2015. DOI : 10.1186/s13638-015-0350-1.
M. Owaida; G. Falcao; J. Andrade; C. Antonopoulos; N. Bellas et al. : Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs; Acm Transactions On Embedded Computing Systems. 2015. DOI : 10.1145/2656207.
A. Teman; R. Visotsky : A Fast Modular Method for True Variation-Aware Separatrix Tracing in Nanoscaled SRAMs; Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 2015. DOI : 10.1109/TVLSI.2014.2358699.

Conference Papers

J. M. Wüthrich; A. K. Balatsoukas Stimming; A. P. Burg : An FPGA-based Accelerator for Rapid Simulation of SC Decoding of Polar Codes. 2015. 2015 IEEE International Conference on Electronics, Circuits, and Systems, Cairo, Egypt, December 6-9, 2015.
N. A. Preyss; A. Burg : Digital Synchronization for Symbol-spaced IEEE802.11ad Gigabit mmWave Systems. 2015. 2015 22nd IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Cairo, Egypt, December 06-09, 2015. p. 637-640.
N. Preyss; S. Rodriguez Egea; A. Burg : Energy-Proportional Single-Carrier Frequency Domain Equalization for mmWave Wireless Communication. 2015. 49th Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, USA, November 8-11, 2015.
N. A. Preyss; C. C. S. D. Senning; A. P. Burg; W.-C. Liu; C.-Y. Liu et al. : A 3.52 Gb/s mmWave Baseband with Delayed Decision Feedback Sequence Estimation in 40 nm. 2015. 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC), Xiamen, Fujian, China, November 9-11, 2015. p. 193-196.
S. Brenna; L. Bettini; A. Bonetti; A. Bonfanti; A. Lacaita : Fundamental Power Limits of SAR and ΔΣ Analog-to-Digital Converters. 2015. IEEE Nordic Circuits and Systems Conference (NORCAS), Oslo, October 2015. DOI : 10.1109/NORCHIP.2015.7364387.
A. Austin; O. Afisiadis; A. Balatsoukas-Stimming; A. Burg : Concurrent Spectrum Sensing and Transmission for Cognitive Radio using Self-Interference Cancellation. 2015. 16th ACM International Symposium on Mobile Ad Hoc Networking and Computing, Hangzhou, China, 22-25 06 2015. p. 407-408. DOI : 10.1145/2746285.2764932.
N. A. Preyss; L. Koester; A. P. Burg : Fractionally Spaced Complex Sub-Nyquist Sampling for Multi-Gigabit 60 GHz Wireless Communication. 2015. Midwest Symposium on Circuits and Systems, Fort Collins, Colorado, USA, August 2-5, 2015.
S. Ganapathy; A. S. Teman; R. Giterman; A. P. Burg; G. Karakonstantis : Approximate Computing With Unreliable Dynamic Memories. 2015. International New Circuits And Systems Conference (NEWCAS), Grenoble, France, June 7-10, 2015.
A. S. Teman; G. Karakonstantis; A. P. Burg; R. Giterman; P. A. Meinerzhagen : Energy versus Data Integrity Trade-Offs in Embedded High-Density Logic Compatible Dynamic Memories. 2015. DATE 2015, Grenoble, France, March 9-13, 2015.
S. Ganapathy; G. Karakonstantis; A. S. Teman; A. P. Burg : Mitigating the Impact of Faults in Unreliable Memories For Error-Resilient Applications. 2015. Design Automation Conference (DAC'15), San Francisco, California, USA, June 7-11, 2015. p. 1-6. DOI : 10.1145/2744769.2744871.
A. Bonetti; A. S. Teman; A. P. Burg : An Overlap-Contention Free True-Single-Phase Clock Dual-Edge-Triggered Flip-Flop. 2015. IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, May, 2015. DOI : 10.1109/ISCAS.2015.7169017.
P. A. Meinerzhagen; A. Bonetti; G. Karakonstantis; C. Roth; F. K. Gürkaynak et al. : Refresh-Free Dynamic Standard-Cell Based Memories: Application to a QC-LDPC Decoder. 2015. IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, May, 2015. DOI : 10.1109/ISCAS.2015.7168911.
J. H.-F. Constantin; L. Wang; G. Karakonstantis; A. Chattopadhyay; A. P. Burg : Exploiting Dynamic Timing Margins in Microprocessors for Frequency-Over-Scaling with Instruction-Based Clock Adjustment. 2015. The Design, Automation and Test in Europe (DATE), Grenoble, France, March 9-13, 2015.

Posters

A. Bonetti; J. H.-F. Constantin; A. S. Teman; A. P. Burg : Circuits and Techniques for Dynamic Timing Monitoring in Microprocessors ; Nanotera Annual Meeting 2015, Bern, Switzerland, May 5, 2015.

Patents

G. Karakonstantis; A. Sankaranarayanan; A. Burg; S. Murali; D. Atienza Alonso ; Method and apparatus for low complexity spectral analysis of bio-signals. US9760536 ; US2015220486 ; EP2884884 ; WO2014027329 . 2015.

Student Projects

A. Gianarda : Power analysis and optimization of on-board processing for the EFM32 microprocessor ; 2015.
B. Steinmann : Automated Performance Characterization of Dynamic Clock Adjustment Techniques on an OpenRISC ISS ; 2015.

2014

Journal Articles

D. S. Nikolopoulos; H. Vandierendonck; N. Bellas; C. D. Antonopoulos; S. Lalis et al. : Energy Efficiency through Significance-Based Computing; Computer. 2014.
A. Balatsoukas-Stimming; A. J. Raymond; W. J. Gross; A. Burg : Hardware Architecture for List Successive Cancellation Decoding of Polar Codes; Ieee Transactions On Circuits And Systems Ii-Express Briefs. 2014. DOI : 10.1109/Tcsii.2014.2327336.
H. Dagan; A. Shapira; A. Teman; A. Mordakhay; S. Jameson et al. : A Low-Power Low-Cost 24 GHz RFID Tag With a C-Flash Based Embedded Memory; Ieee Journal Of Solid-State Circuits. 2014. DOI : 10.1109/Jssc.2014.2323352.
I. Kazi; P. Meinerzhagen; P.-E. Gaillardon; D. Sacchetto; Y. Leblebici et al. : Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design; IEEE Transactions on Circuits and Systems Part 1 Regular Papers. 2014. DOI : 10.1109/TCSI.2014.2334891.
A. Teman; P. Meinerzhagen; R. Giterman; A. Fish; A. Burg : Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM; Ieee Transactions On Circuits And Systems Ii-Express Briefs. 2014. DOI : 10.1109/Tcsii.2014.2305016.
A. Balatsoukas-Stimming; A. P. Burg : Density Evolution for Min-Sum Decoding of LDPC Codes Under Unreliable Message Storage; IEEE Communications Letters. 2014. DOI : 10.1109/Lcomm.2014.030714.132830.
F. Moradi; G. Panagopoulos; G. Karakonstantis; H. Farkhani; D. T. Wisland et al. : Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology; Microelectronics Journal. 2014. DOI : 10.1016/j.mejo.2013.09.009.
C. Senning; L. Bruderer; J. Hunziker; A. Burg : A Lattice Reduction-Aided MIMO Channel Equalizer in 90 nm CMOS Achieving 720 Mb/s; IEEE Transactions on Circuits and Systems I. 2014. DOI : 10.1109/TCSI.2013.2295027.
N. Walenta; A. P. Burg; D. Caselunghe; J. H.-F. Constantin; N. Gisin et al. : A Fast and Versatile Quantum Key Distribution System with Hardware Key Distillation and Wavelength Multiplexing; New Journal of Physics. 2014. DOI : 10.1088/1367-2630/16/1/013047.

Conference Papers

A. Balatsoukas-Stimming; G. Karakonstantis; A. Burg : Enabling Complexity-Performance Trade-Offs for Successive Cancellation Decoding of Polar Codes. 2014. IEEE International Symposium on Information Theory (ISIT), Honolulu, HI, JUN 29-JUL 04, 2014. p. 2977-2981.
L. Atias; A. Teman; A. Fish : Single event upset mitigation in low power SRAM design. 2014. 2014 IEEE 28th Convention of Electrical & Electronics Engineers in Israel (IEEEI), Eilat, Israel, 3-5 December 2014. p. 1-5. DOI : 10.1109/EEEI.2014.7005796.
C. Senning; M. Mendicute; A. Burg : Cross Layer Energy-Efficiency Optimization For Cognitive Radio Transceivers. 2014. [IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)', u'IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)'].
G. Kail; P. Maechler; N. Preyss; A. Burg : Robust Asynchronous Indoor Localization Using Led Lighting. 2014. IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Florence, ITALY, MAY 04-09, 2014.
N. A. Preyss; R. Pantic; A. P. Burg : Correlation Based Phase Noise Compensation in 60 GHz Wireless Systems. 2014. 2014 IEEE 28-th Convention of Electrical and Electronics Engineers in Israel, Eilat, Israel, December, 3-5, 2014.
A. Teman : Dynamic stability and noise margins of SRAM arrays in nanoscaled technologies. 2014. 2014 IEEE Faible Tension Faible Consommation (FTFC), Monaco, Monaco, 4-6 May 2014. p. 1-5. DOI : 10.1109/FTFC.2014.6828617.
R. Giterman; A. Teman; P. Meinerzhagen; A. Burg; A. Fish : 4T Gain-Cell with internal-feedback for ultra-low retention power at scaled CMOS nodes. 2014. 2014 IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne VIC, Australia, 1-5 June 2014. p. 2177-2180. DOI : 10.1109/ISCAS.2014.6865600.
S. Ganapathy; G. Karakonstantis; R. Canal; A. P. Burg : Variability-Aware Design Space Exploration of Embedded Memories. 2014. 28th IEEE Convention of Electrical and Electronics Engineers in Israel, Eilat, Israel, December 3-5, 2014.
R. Braojos Lopez; I. Beretta; J. H.-F. Constantin; A. P. Burg; D. Atienza Alonso : A Wireless Body Sensor Network For Activity Monitoring With Low Transmission Overhead. 2014. The 12th IEEE International Conference on Embedded and Ubiquitous Computing, Milan, 25-29.08.2014.
A. Balatsoukas-Stimming; M. Bastani Parizi; A. P. Burg : LLR-based Successive Cancellation List Decoding of Polar Codes. 2014. IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2014), Florence, Italy, May 4-9, 2014.
A. Balatsoukas-Stimming; G. Karakonstantis; A. P. Burg : Enabling Complexity-Performance Trade-Offs for Successive Cancellation Decoding of Polar Codes. 2014. IEEE International Symposium on Information Theory, Honolulu, Hawaii, USA, June 29 - July 4, 2014.
M. Yousefbeiki; P. Belanovic; A. P. Burg; J. Perruisseau-Carrier : True MIMO transmission using a single RF-chain and antenna: recent developments. 2014. Eucap 2014, 8th European Conf. on Antennas and Prop., The Hague, Netherlands, 2014.
G. Karakonstantis; A. Sankaranarayanan; M. M. S. Aly; D. Atienza Alonso; A. P. Burg : A Quality-Scalable and Energy-Efficient Approach for Spectral Analysis of Heart Rate Variability. 2014. Design Automation & Test in Europe (DATE), Dresden, Germany.
L. Amarù; P.-E. Gaillardon; A. Burg; G. De Micheli : Data Compression via Logic Synthesis. 2014. 19th Asia and South Pacific Design Automation Conference (ASP-DAC 2014), Singapore, January 20-23, 2014. p. 628-633. DOI : 10.1109/ASPDAC.2014.6742961.

Theses

C. C. S. D. Senning / A. P. Burg (Dir.) : Energy Efficient VLSI Circuits for MIMO-WLAN. Lausanne, EPFL, 2014. DOI : 10.5075/epfl-thesis-6386.
P. A. Meinerzhagen / A. P. Burg; Y. Leblebici (Dir.) : Novel Approaches Toward Area- and Energy-Efficient Embedded Memories. Lausanne, EPFL, 2014. DOI : 10.5075/epfl-thesis-6074.

Posters

L. Amarù; A. Balatsoukas Stimming; P.-E. Gaillardon; A. Burg; G. De Micheli : Restructuring of Arithmetic Circuits with Biconditional Binary Decision Diagrams ; University Booth at DATE 2014, Dresden, Germany, March 24-28, 2014.
V. Camus; G. Karakonstantis; J. Schlachter; A. P. Burg; C. Enz : Cross-Layer Inexact Design for Low-Power Applications ; NanoTera Annual Meeting, Lausanne, Switzerland.

Patents

A. Y. Dogan; J. Constantin; A. Burg; D. Atienza Alonso ; Ultra-Low Power Multicore Architecture For Parallel Biomedical Signal Processing. WO2013136259 ; WO2013136259 . 2014.

Student Projects

E. A. Pignat : Retention Time Characterization of Commercial DRAM Modules Using an FPGA-based Test Platform ; 2014.
L. F. Schmid : Low Power Wake-up Receiver ; 2014.
J. Liu : RSS Range Estimation for Indoor Localization Using LED Lighting ; 2014.

2013

Journal Articles

A. Burg; A. Teman; A. Fish; P. Meinerzhagen : Impact of body biasing on the retention time of gain-cell memories; The Journal of Engineering. 2013. DOI : 10.1049/joe.2013.0057.
P. A. Meinerzhagen; A. Teman; R. Giterman; A. P. Burg; A. Fish : Exploration of Sub-VT and Near-VT 2T Gain-Cell Memories for Ultra-Low Power Applications under Technology Scaling; Journal of Low Power Electronics and Applications. 2013. DOI : 10.3390/jlpea3020054.

Conference Papers

C. C. S. D. Senning; A. P. Burg : Block-Floating-Point Enhanced MMSE Filter Matrix Computation for MIMO-OFDM Communication Systems. 2013. 2013 IEEE International Conference on Electronics, Circuits, and Systems, Abu Dhabi, UAE, December 8-11, 2013.
A. Balatsoukas-Stimming; P. Belanovic; K. Alexandris; A. Burg : On Self-interference Suppression Methods for Low-complexity Full-duplex MIMO. 2013. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, November 3-6, 2013.
R. Cojbasic; Ö. Cogal; P. A. Meinerzhagen; C. C. S. D. Senning; C. J. Slater et al. : FireBird: PowerPC e200 Based SoC for High Temperature Operation. 2013. IEEE Custom Integrated Circuits Conference (CICC), San Jose, California, USA, September 23-25, 2013.
S. Zwicky; C. Benkeser; A. P. Burg; Q. Huang : Efficient VLSI Implementation of Reduced-State Sequence Estimation for Wireless Communications. 2013. 38th International Conference on Acoustics, Speech, and Signal Processing (ICASSP), Vancouver, Canada, May 26-31, 2013.
I. Kazi; P. A. Meinerzhagen; P.-E. J. M. Gaillardon; D. Sacchetto; A. P. Burg et al. : A ReRAM-Based Non-Volatile Flip-Flop with Sub-VT Read and CMOS Voltage-Compatible Write. 2013. 11th IEEE International NEWCAS Conference, Paris, France, June 16-19, 2013.
A. Balatsoukas Stimming; N. Preyss; A. Cevrero; A. Burg; C. Roth : A Parallelized Layered QC-LDPC Decoder for IEEE 802.11ad. 2013. 11th IEEE International NEWCAS Conference, Paris, France, June 16-19, 2013. DOI : 10.1109/NEWCAS.2013.6573590.
A. Cevrero; N. Evmorfopoulos; C. Antoniadis; P. Ienne; Y. Leblebici et al. : Fast and Accurate BER Estimation Methodology for I/O Links based on Extreme Value Theory. 2013. Design, Automation & Test in Europe Conference (DATE 2013), Grenoble, France, March 18-22, 2013.
A. Y. Dogan; R. Braojos Lopez; J. H.-F. Constantin; G. Ansaloni; A. P. Burg et al. : Synchronizing Code Execution on Ultra-Low-Power Embedded Multi-Channel Signal Analysis Platforms. 2013. The Design, Automation and Test in Europe (DATE), 2013, Grenoble, France.

Theses

A. Y. Dogan / D. Atienza Alonso; A. P. Burg (Dir.) : Energy-Aware Processing Platform Exploration for Embedded Biosignal Analysis. Lausanne, EPFL, 2013. DOI : 10.5075/epfl-thesis-5701.

Book Chapters

J. H.-F. Constantin; A. Dogan; O. Andersson; P. A. Meinerzhagen; J. Rodrigues et al. : An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing; VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design; Springer, 2013. p. 88-106.

Posters

P. Belanovic; A. Balatsoukas-Stimming; A. Burg : A Multipurpose Testbed for Full-Duplex Wireless Communications ; International Conference on Electronics, Circuits, and Systems, Abu Dhabi, UAE, December 8-11 2013.
J. H.-F. Constantin : Application-Specific Processor Design for Low-Complexity & Low-Power Embedded Systems ; Winter School on Design Technologies for Heterogeneous Embedded Systems (FETCH), Leysin, Vaud, Switzerland, January 7-9, 2013.

Talks

A. P. Burg : Near- and Sub-Threshold Design for Ultra-Low-Power Embedded Systems ; Winter School on Design Technologies for Heterogeneous Embedded Systems (FETCH), Leysin, Vaud, Switzerland, January 7-9, 2013.

2012

Journal Articles

P. Belanovic; S. Valcarcel Macua; S. Zazo : Distributed static linear Gaussian models using consensus; Neural Networks. 2012. DOI : 10.1016/j.neunet.2012.07.004.
A. Y. Dogan; J. H.-F. Constantin; D. Atienza Alonso; A. P. Burg; L. Benini : Low-power processor architecture exploration for online biomedical signal analysis; Circuits, Devices & Systems, IET. 2012. DOI : 10.1049/iet-cds.2012.0011.
P. Maechler; C. Studer; D. Bellasi; A. Maleki; A. P. Burg et al. : VLSI Design of Approximate Message Passing for Signal Restoration and Compressive Sensing; IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 2012. DOI : 10.1109/JETCAS.2012.2214636.
G. Karakonstantis; D. Mohapatra; K. Roy : Logic and Memory Design Based on Unequal Error Protection for Voltage-scalable, Robust and Adaptive DSP Systems; Journal Of Signal Processing Systems For Signal Image And Video Technology. 2012. DOI : 10.1007/s11265-011-0631-9.
P. Greisen; M. Schaffner; S. Heinzle; M. Runo; A. Smolic et al. : Analysis and VLSI Implementation of EWA Rendering for Real-Time HD Video Applications; IEEE Transactions on Circuits and Systems for Video Technology. 2012. DOI : 10.1109/Tcsvt.2012.2201671.

Conference Papers

S. Belfanti; C. Benkeser; K. Badawi; Q. Huang; A. P. Burg : Successive Interference Cancellation for 3G Downlink: Algorithm and VLSI Architecture. 2012. IEEE/IFIP International Conference on Very Large Scale Integration (VLSI-SoC), Santa Cruz, CA, USA, October 7-10, 2012.
H. Kröll; S. Zwicky; C. Benkeser; Q. Huang; A. P. Burg : Low-complexity Frequency Synchronization for GSM Systems: Algorithms and Implementation. 2012. International Conference on Ultra Modern Telecommunications (ICUMT), St. Petersburg, Russia, October 3-5, 2012.
C. Roth; C. Benkeser; C. Studer; G. Karakonstantis; A. P. Burg : Data Mapping for Unreliable Memories. 2012. 50th Annual Allerton Conference on Communication, Control, and Computing, October, 1-5, 2012.
G. Falcao Fernandes; D. Novo Bruna; M. Purnaprajna; N. Bellas; C. Antonopoulos et al. : Shortening design time through multiplatform simulations with a portable OpenCL golden-model: the LDPC decoder case. 2012. IEEE 20th International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2012.
G. Karakonstantis; A. Sankaranarayanan; A. P. Burg : Low Complexity Spectral Analysis of Heart-Rate-Variability through a Wavelet Based FFT. 2012. IEEE Computing in Cardiology (CinC), September, 2012.
M. M. S. Aly; G. Karakonstantis; D. Atienza Alonso; A. P. Burg : Design of Energy Efficient and Dependable Health Monitoring Systems under Unreliable Nanometer Technologies. 2012. 7th International Conference on Body Area Networks (BodyNets ’12), Oslo, Norway, September 24-26 2012. p. 52-58. DOI : 10.4108/icst.bodynets.2012.249935.
J. H.-F. Constantin; A. Y. Dogan; O. Andersson; P. A. Meinerzhagen; J. N. Rodrigues et al. : TamaRISC-CS: An Ultra-Low-Power Application-Specific Processor for Compressed Sensing. 2012. IFIP/IEEE 20th International Conference on Very Large Scale Integration (VLSI-SoC), Santa Cruz, USA, October 7-10, 2012.
N. A. Preyss; C. Studer; A. P. Burg : Layered Detection and Decoding in MIMO Wireless Systems. 2012. Conference on Design and Architectures for Signal and Image Processing (DASIP) 2012, Karlsruhe, Germany, October 23-25, 2012.
P. A. Meinerzhagen; A. Teman; A. Mordakhay; A. P. Burg; A. Fish : A Sub-VT 2T Gain-Cell Memory for Biomedical Applications. 2012. IEEE Subthreshold Microelectronics Conference, Boston, Massachusetts, USA, October 9-10, 2012.
P. A. Meinerzhagen; J. N. Rodrigues; A. P. Burg : Standard-Cell Based Memories (SCMs): from Sub-VT to Error-Resilient Systems. 2012. IEEE International Solid-State Circuits Conference (ISSCC), Student Research Preview (SRP) session, San Francisco, California, USA, February 17-21, 2012.
R. Iqbal; P. A. Meinerzhagen; A. P. Burg : Two-Port Low-Power Gain-Cell Storage Array: Voltage Scaling and Retention Time. 2012. IEEE International Symposium on Circuits and Systems (ISCAS), Seoul, Korea, May 20-23, 2012.
M. U. Khalid; P. A. Meinerzhagen; A. P. Burg : Replica Bit-Line Technique for Embedded Multilevel Gain-Cell DRAM. 2012. IEEE International NEWCAS Conference, Montréal, Canada, June 17-20, 2012. p. 77-80.
P. A. Meinerzhagen; O. Andersson; B. Mohammadi; Y. Sherazi; A. P. Burg et al. : A 500 fW/bit 14 fJ/bit-access 4kb Standard-Cell Based Sub-VT Memory in 65nm CMOS. 2012. IEEE European Solid-State Circuits Conference (ESSCIRC), Bordeaux, September 17-21, 2012.
F. Borlenghi; E. M. Witte; G. Ascheid; H. Meyr; A. P. Burg : A 2.78 mm2 65 nm CMOS Gigabit MIMO Iterative Detection and Decoding Receiver. 2012. 38th European Solid-State Circuits Conference, Bordeaux, France, September 17-21, 2012.
G. Karakonstantis; C. Roth; C. Benkeser; A. Burg : On the Exploitation of the Inherent Error Resilience of Wireless Systems under Unreliable Silicon. 2012. IEEE Design Automation Conference (DAC), San Francisco, June 3-7, 2012. p. 510-515.
J. H.-F. Constantin; A. P. Burg; F. K. Gurkaynak : Instruction Set Extensions for Cryptographic Hash Functions on a Microcontroller Architecture. 2012. 23rd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Delft, The Netherlands, July 9-11, 2012. p. 117-124.
A. Y. Dogan; J. H.-F. Constantin; M. Ruggiero; A. P. Burg; D. Atienza Alonso : Multi-Core Architecture Design for Ultra-Low-Power Wearable Health Monitoring Systems. 2012. IEEE/ACM 2012 Design Automation and Test in Europe conference (DATE), Dresden, Germany, March 12-16, 2012. p. 988-994.

Reviews

A. Teman; P. A. Meinerzhagen; A. P. Burg; A. Fish : Review and Classification of Gain Cell eDRAM Implementations; IEEE Convention of Electrical and Electronics Engineers in Israel (IEEEI). 2012.

Book Chapters

C. Studer; M. Wenk; A. Burg : VLSI Implementation of Hard- and Soft-Output Sphere Decoding for Wide-Band MIMO Systems; VLSI-SoC: Forward-Looking Trends in IC and Systems Design; Berlin, Heidelberg: Springer Berlin Heidelberg, 2012. p. 128-154.

Working Papers

J. H.-F. Constantin; A. P. Burg; F. K. Gurkaynak : Investigating the Potential of Custom Instruction Set Extensions for SHA-3 Candidates on a 16-bit Microcontroller Architecture. 2012.

Talks

N. Walenta; A. P. Burg; J. H.-F. Constantin; N. Gisin; O. Guinnard et al. : 1 Mbps coherent one-way QKD with dense wavelength division multiplexing and hardware key distillation ; 2nd Annual Conference on Quantum Cryptography (QCRYPT 2012), Singapore, September 10th-14th, 2012.

Student Projects

C. Iliopoulos : Building a visible light communication system ; 2012.

2011

Journal Articles

P. A. Meinerzhagen; S. M. Y. Sherazi; A. P. Burg; J. N. Rodrigues : Benchmarking of standard-cell based memories in the sub-VT domain in 65-nm CMOS technology; IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 2011. DOI : 10.1109/JETCAS.2011.2162159.
P. Greisen; S. Heinzle; M. Gross; A. P. Burg : An FPGA-based processing pipeline for high definition stereo video; EURASIP Journal on Image and Video Processing. 2011. DOI : 10.1186/1687-5281-2011-18.

Conference Papers

G. Karakonstantis; N. Bellas; C. Antonopoulos; G. Tziantzioulis; V. Gupta et al. : Significance Driven Computation on Next-Generation Unreliable Platforms. 2011. 48th ACM/IEEE/EDAC Design Automation Conference (DAC), San Diego, CA, Jun 05-09, 2011. p. 290-291.
F. Borlenghi; E. M. Witte; G. Ascheid; H. Meyr; A. P. Burg : A 772 Mbit/s 8.81 bit/nJ 90 nm CMOS Soft-Input Soft-Output Sphere Decoder. 2011. IEEE Asian Solid-State Circuits Conference, Jeju, Korea, November 14-16, 2011.
P. Maechler; N. Felber; A. P. Burg : Random Sampling ADC for Sparse Spectrum Sensing. 2011. European Signal Processing Conference, Barcelona, Spain, August 29 - September 2, 2011.
S. Heinzle; P. Greisen; D. Gallup; C. Chen; D. Saner et al. : Computational stereo camera system with programmable control loop. 2011. ACM SIGGRAPH , Vancouver, Canada, August 7-11, 2011. p. 1. DOI : 10.1145/2010324.1964989.
C. Studer; M. Wenk; A. P. Burg : System-level implications of residual transmit-RF impairments in MIMO systems. 2011. European Conference on Antennas and Propagation, Rome, Italy, April 11-15, 2011. p. 2686-2689.
P. A. Meinerzhagen; O. Andersson; Y. Sherazi; A. P. Burg; J. Rodrigues : Synthesis strategies for sub-VT systems. 2011. IEEE European Conference on Circuit Theory and Design (ECCTD), Linköping, Sweden, August 29-31, 2011. p. 552-555. DOI : 10.1109/ECCTD.2011.6043593.
C. Roth; A. Cevrero; C. Studer; Y. Leblebici; A. Burg : Area, throughput, and energy-efficiency trade-offs in the VLSI implementation of LDPC decoders. 2011. IEEE International Symposium on Circuits and Systems (ISCAS), Rio de Janeiro, Brazil, May 15-18, 2011. p. 1772-1775. DOI : 10.1109/ISCAS.2011.5937927.
P. A. Meinerzhagen; O. Andiç; J. Treichler; A. P. Burg : Design and failure analysis of logic-compatible multilevel gain-cell-based DRAM for fault-tolerant VLSI systems. 2011. IEEE 21st Edition of the Great Lakes Symposium on VLSI (GLSVLSI), Lausanne, Switzerland, May 2-4, 2011. p. 343-346. DOI : 10.1145/1973009.1973078.
A. Y. Dogan; D. Atienza Alonso; A. P. Burg; I. Loi; L. Benini : Power/Performance Exploration of Single-core and Multi-core Processor Approaches for Biomedical Signal Processing. 2011. Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS ‘11), Madrid, Spain, September 26-29, 2011. p. 102-111.

2010

Journal Articles

P. Greisen; S. Haene; A. Burg : Simulation and Emulation of MIMO Wireless Baseband Transceivers; Eurasip Journal On Wireless Communications And Networking. 2010. DOI : 10.1155/2010/196796.

Conference Papers

C. Novak; C. Studer; A. Burg; G. Matz : The effect of unreliable LLR storage on the performance of MIMO-BICM. 2010. 2010 44th Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, USA, 7-10 November 2010. p. 736-740. DOI : 10.1109/ACSSC.2010.5757661.
C. Senning; A. Staudacher; A. Burg : Systolic-array based regularized QR-decomposition for IEEE 802.11n compliant soft-MMSE detection. 2010. 2010 International Conference on Microelectronics (ICM), Cairo, Egypt, 19-22 December 2010. p. 391-394. DOI : 10.1109/ICM.2010.5696169.
L. Bruderer; C. Senning; A. Burg : Low-complexity Seysen's algorithm based lattice reduction-aided MIMO detection for hardware implementations. 2010. 2010 44th Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, USA, 7-10 November 2010. p. 1468-1472. DOI : 10.1109/ACSSC.2010.5757780.
M. Wenk; L. Bruderer; A. Burg; C. Studer : Area- and throughput-optimized VLSI architecture of sphere decoding. 2010. 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC), Madrid, Spain, 27-29 09 2010. p. 189-194. DOI : 10.1109/VLSISOC.2010.5642593.
P. Maechler; P. Greisen; N. Felber; A. Burg : Matching pursuit: Evaluation and implementatio for LTE channel estimation. 2010. 2010 IEEE International Symposium on Circuits and Systems - ISCAS 2010, Paris, France, 30 05 - 2 06 2010. p. 589-592. DOI : 10.1109/ISCAS.2010.5537528.
C. Studer; M. Wenk; A. Burg : MIMO transmission with residual transmit-RF impairments. 2010. 2010 International ITG Workshop on Smart Antennas (WSA), Bremen, Germany, 23-24 02 2010. p. 189-196. DOI : 10.1109/WSA.2010.5456453.
C. Roth; P. A. Meinerzhagen; C. Studer; A. P. Burg : A 15.8 pJ/bit/iter quasi-cyclic LDPC decoder for IEEE 802.11n in 90 nm CMOS. 2010. 2010 IEEE Asian Solid-State Circuits Conference (A-SSCC), Beijing, China, November 8-10, 2010. p. 1-4. DOI : 10.1109/ASSCC.2010.5716618.
P. A. Meinerzhagen; C. Roth; A. P. Burg : Towards generic low-power area-efficient standard cell based memory architectures. 2010. 2010 53rd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Seattle, WA, USA, August 1-4, 2010. p. 129-132. DOI : 10.1109/MWSCAS.2010.5548579.
L. Bruderer; C. Studer; M. Wenk; D. Seethaler; A. Burg : VLSI Implementation of a Low-Complexity LLL Lattice Reduction Algorithm for MIMO Detection. 2010. International Symposium on Circuits and Systems Nano-Bio Circuit Fabrics and Systems (ISCAS 2010), Paris, FRANCE, May 30-Jun 02, 2010. p. 3745-3748.

2009

Journal Articles

C. Benkeser; A. Burg; T. Cupaiuolo; Q. Huang : Design and Optimization of an HSDPA Turbo Decoder ASIC; IEEE Journal of Solid-State Circuits. 2009. DOI : 10.1109/JSSC.2008.2007166.

Conference Papers

S. Eberli; A. P. Burg; W. Fichtner : Implementation of a 2x2 MIMO-OFDM receiver on an application specific processor. 2009. International Conference on Microelectronics, Cairo, EGYPT, Dec 29-31, 2007. p. 1642-1649. DOI : 10.1016/j.mejo.2009.02.005.
A. Burg; S. Haene; M. Borgmann; D. Baum; T. Thaler et al. : A 4-Stream 802.11n Baseband Transceiver in 0.13 mu m CMOS. 2009. Symposium on VLSI Circuits, Kyoto, JAPAN, Jun 16-18, 2009. p. 228-229.
A. Burg; S. Haene; M. Borgmann; D. Baum; T. Thaler et al. : A 4-Stream 802.11n Baseband Transceiver in 0.13 mu m CMOS. 2009. Symposium on VLSI Circuits, Kyoto, JAPAN, Jun 16-18, 2009. p. 282-283.

2008

Journal Articles

S. Haene; D. Perels; A. Burg : A real-time 4-stream MIMO-OFDM transceiver: System design, FPGA implementation, and characterization; Ieee Journal On Selected Areas In Communications. 2008. DOI : 10.1109/JSAC.2008.080805.

Conference Papers

C. Senning; C. Studer; P. Luethi; W. Fichtner : Hardware-efficient steering matrix computation architecture for MIMO communication systems. 2008. IEEE International Symposium on Circuits and Systems, 2008. ISCAS 2008., Seattle, WA, USA, May 18-21 2008. p. 304-307. DOI : 10.1109/ISCAS.2008.4541415.
C. Studer; N. A. Preyss; C. Roth; A. Burg : Configurable High-Throughput Decoder Architecture for Quasi-Cyclic LDPC Codes. 2008. 42nd Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, Oct 26-29, 2008. p. 1137-1142.
C. Benkeser; A. Burg; T. Cupaiuolo; Q. Huang : A 58mW 1.2 mm 2 HSDPA Turbo Decoder ASIC in 0.13 μm CMOS. 2008. IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb 03-07, 2008. DOI : 10.1109/ISSCC.2008.4523158.
C. Studer; A. Burg; H. Boelcskei : Soft-output sphere decoding: Algorithms and VLSI implementation. 2008. 40th Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, Oct 29-Nov 02, 2006. p. 290-300. DOI : 10.1109/JSAC.2008.080206.

2007

Conference Papers

S. Eberli; A. Burg; T. Boesch; W. Fichtner : An IEEE 802.11a baseband receiver implementation on an application specific processor. 2007. 50th Midwest Symposium on Circuits and Systems, Montreal, CANADA, Sep 05, 2007-Aug 08, 2008. p. 1066-1069.
A. Burg; S. Haene; W. Fichtner; M. Rupp : Regularized frequency domain equalization algorithm and its VLSI implementation. 2007. IEEE International Symposium on Circuits and Systems, New Orleans, LA, May 27-30, 2007. p. 3530-3533.
P. Luethi; A. Burg; S. Haene; D. Perels; N. Felber et al. : VLSI implementation of a high-speed iterative sorted MMSE QR decomposition. 2007. IEEE International Symposium on Circuits and Systems, New Orleans, LA, May 27-30, 2007. p. 1421-1424.
S. Haene; A. Burg; R. Luethi; N. Felber; W. Fichtner : FFT processor for OFDM channel estimation. 2007. IEEE International Symposium on Circuits and Systems, New Orleans, LA, May 27-30, 2007. p. 1417-1420.
A. Burg; D. Seethaler; G. Matz : VLSI implementation of a lattice-reduction algorithm for multi-antenna broadcast precoding. 2007. IEEE International Symposium on Circuits and Systems, New Orleans, LA, May 27-30, 2007. p. 673-676.

2006

Conference Papers

C. Studer; A. Burg; W. Fichtner : A unification of ML-optimal tree-search decoders. 2006. 40th Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, Oct 29-Nov 01, 2006. p. 2185-2189.
C. Studer; M. Wenk; A. Burg; H. Bolsckei : Soft-output sphere decoding: Performanceand implementation aspects. 2006. 40th Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, Oct 29-Nov 01, 2006. p. 2071-2076.
D. Perels; S. Haene; A. Burg; P. Luethi; N. Felber et al. : A frame-start detector for a 4x4 MIMO-OFDM system. 2006. 31st IEEE International Conference on Acoustics, Speech and Signal Processing, Toulouse, FRANCE, May 14-19, 2006. p. 4095-4098.
M. Wenk; A. Burg; M. Zellweger; C. Studer; W. Fichtner : VLSI implementation of the list sphere algorithm. 2006. 24th Norchip Conference, Linkoping, SWEDEN, Nov 20-21, 2006. p. 107-110.
A. Burg; S. Haene; D. Perels; P. Luethi; N. Felber et al. : Algorithm and VLSI architecture for linear MMSE detection in MIMO-OFDM systems. 2006. IEEE International Symposium on Circuits and Systems, Kos Isl, GREECE, May 21-24, 2006. p. 4102-4105.
S. Haene; A. Burg; D. Perels; P. Luethi; N. Felber et al. : Silicon implementation of an MMSE-based soft demapper for MIMO-BICM. 2006. IEEE International Symposium on Circuits and Systems, Kos Isl, GREECE, May 21-24, 2006. p. 2597-2600.
M. Wenk; M. Zellweger; A. Burg; N. Felber; W. Fichtner : K-Best MIMO detection VLSI architectures achieving up to 424 mbps. 2006. IEEE International Symposium on Circuits and Systems, Kos Isl, GREECE, May 21-24, 2006. p. 1151-1154.
D. Perels; S. Haene; A. Burg; P. Luethi; N. Felber et al. : A frame-start detector for a 4 x 4 MIMO-OFDM system. 2006. 31st IEEE International Conference on Acoustics, Speech and Signal Processing, Toulouse, FRANCE, May 14-19, 2006. p. 425-+.
A. Burg; M. Borgmann; M. Wenk; C. Studer; H. Boelcskei : Advanced receiver algorithms for MIMO wireless communications. 2006. Design, Automation and Test in Europe Conference and Exhibition (DATE 06), Munich, GERMANY, Mar 06-10, 2006. p. 591-596.

2005

Conference Papers

S. Haene; A. Burg; D. Perels; P. Luethi; N. Felber et al. : FPGA implementation of Viterbi decoders for MIMO-BICM. 2005. 39th Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, Oct 30-Nov 02, 2005. p. 734-738.
S. Haene; P. Luethi; A. Burg; N. Felber; W. Fichtner et al. : ASIC implementation of a MIMO-OFDM transceiver for 192 Mbps WLANs. 2005. 31st European Solid-State Circuits Conference, Grenoble, FRANCE, Sep 12-16, 2005. p. 215-218.
S. Haene; D. Perels; P. Luethi; N. Felber; W. Fichtner et al. : Receiver design for multi-antenna wireless communications. 2005. International Conference on PhD Research in Microelectronics and Electronics (PRIME 2005), Lausanne, SWITZERLAND, 2005. p. 231-234.
M. Borgmann; H. Bolcskei; J. Hansen; A. Burg; D. Cescato : Interpolation-based QR decomposition in MIMO-OFDM systems. 2005. 6th IEEE Workshop on Signal Processing Advances in Wireless Communications, New York, NY, Jun 05-08, 2005. p. 945-949.
M. Borgmann; M. Wenk; M. Zellweger; W. Fichtner; H. Bolcskei et al. : VLSI implementation of MIMO detection using the sphere decoding algorithm. 2005. 30th European Solid-State Circuits Conference (ESSCIRC 2004), Leuven, BELGIUM, Sep 21-23, 2004. p. 1566-1577. DOI : 10.1109/JSSC.2005.847505.

2004

Conference Papers

M. Wenk; M. Zellweger; M. Wegmueller; N. Felber; W. Fichtner et al. : VLSI implementation of the sphere decoding algorithm. 2004. 30th European Solid-State Circuits Conference (ESSCIRC 2004), Leuven, BELGIUM, Sep 21-23, 2004. p. 303-306.
M. Rupp; D. Perels; S. Haene; N. Felber; W. Fichtner et al. : Performance of MIMO-extended UMTS-FDD downlink comparing space-time RAKE and linear equalizer. 2004. 58th IEEE Vehicular Technology Conference (VTC 2003), Orlando, FL, Oct 06-09, 2003. p. 473-477.
M. Rupp; S. Haene; D. Perels; N. Felber; W. Fichtner et al. : Low complexity frequency domain equalization of MIMO channels with applications to MIMO-CDMA systems. 2004. 58th IEEE Vehicular Technology Conference (VTC 2003), Orlando, FL, Oct 06-09, 2003. p. 468-472.

2003

Journal Articles

A. Burg; E. Beck; M. Rupp : Rapid prototyping for wireless designs: the five-ones approach; Signal Processing. 2003. DOI : 10.1016/S0165-1684(03)00090-2.

Conference Papers

S. Moser; O. Isler; F. Gurkaynak; A. Burg; N. Felber et al. : Efficient ASIC implementation of a real-time depth mapping stereo vision system. 2003. 46th IEEE International Midwest Symposium on Circuits and Systems, Cairo, EGYPT, Dec 27-30, 2003. p. 1478-1481.
N. Felber; W. Fichtner; A. Burg : A 50 MBPS 4x4 maximum likelihood decoder for multiple-input multiple-output systems with QPSK modulation. 2003. 10th IEEE International Conference on Electronics, Circuits and Systems, Sharjah, U ARAB EMIRATES, Dec 14-17, 2003. p. 332-335.
R. Bischoff; J. Biveroni; M. Bruehwiler; A. Burg; N. Felber et al. : Programmable code processor for software defined radio. 2003. 37th Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, Nov 09-12, 2003. p. 2156-2160.
M. Rupp; N. Felber; W. Fichtner; A. Burg : Practical low complexity linear equalization for MIMO-CDMA systems. 2003. 37th Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, Nov 09-12, 2003. p. 1266-1272.
F. Gurkaynak; H. Kaeslin; W. Fichtner; A. Burg : Variable delay ripple carry adder with carry chain interrupt detection. 2003. IEEE International Symposium on Circuits and Systems, BANGKOK, THAILAND, May 25-28, 2003. p. 113-116.

2002

Conference Papers

M. Sans; A. Burg; W. Fichtner; G. Acunto : An ASIC implementation of adaptive arithmetic coding. 2002. 36th Asilomar Conference on Signals, Systems and Computers, PACIFIC GROVE, CA, Nov 03-06, 2002. p. 1078-1083.

2001

Conference Papers

A. Burg; M. Rupp; E. Beck; S. Das; M. Guillaud : Rapid prototyping design of a 4x4 BLAST-over-UMTS system. 2001. 35th Asilomar Conference on Signals, Systems and Computers, PACIFIC GROVE, CA, Nov 04-07, 2001. p. 1256-1260.

2000

Conference Papers

A. P. Burg; R. Keller; J. Wassner; N. Felber; W. Fichtner : A 3D-DCT real-time video compression system for low complexity single-chip VLSI implementation. 2000. Mobile Multimedia Conference, MoMuC 2000, Tokyo, Japan, November, 2000.
A. Burg; L. Mailaender; B. Haller; M. Rupp; E. Beck et al. : From basic concept to real-time implementation: Prototyping WCDMA downlink receiver algorithms - A case study. 2000. 34th Asilomar Conference on Signals, Systems, and Computers, PACIFIC GROVE, CA, Oct 29-Nov 01, 2000. p. 84-88.