Naresh R. Shanbhag
Jack Kilby Professor of Electrical and Computer Engineering
University of Illinois at Urbana-Champaign
Director: Systems on Nanoscale Information fabriCs (SONIC) Center
Abstract
Computing in the Nanoscale Era – A Shannon-inspired Perspective
Moore’s Law has been the driving force behind the exponential growth in the semiconductor industry for the past five decades years. Today, energy efficiency and reliability challenges in nanoscale CMOS (and beyond CMOS) processes threaten the continuation of Moore’s Law. This talk will describe a Shannon-inspired statistical computing paradigm that seeks to address this issue by treating the problem of computing on unreliable devices and circuits as one of communicating information over an unreliable/noisy channel. Such a paradigm seeks to transform computing from its von Neumann roots in data processing to Shannon-inspired information processing. Key elements of this paradigm are the use of statistical signal processing, machine learning principles, equalization and error-control, for designing error-resilient on-chip computation, communication, storage, and mixed-signal analog front-ends. The talk will provide a historical perspective, demonstrate examples of communications-inspired designs of on-chip subsystems such as low-power filtering, video compression, PN-code acquisition, subthreshold ECG processor, and on/off-chip interconnect. The Shannon-inspired paradigm is being pervasively explored in the recently established SONIC (Systems on Nanoscale Information fabrIcs) Center to include statistical inference in its myriad forms and their application to stochastic information processing, information-based analog mixed-signal interfaces, neuro-principled cognitive computational models, and the design of nanofunctions/nanoprimitives in deeply scaled CMOS and beyond CMOS fabrics. SONIC is funded under the STARnet (the Semiconductor Technology Advanced Research network) program sponsored by the US Department of Defense and U.S. semiconductor and supplier companies and is administered by the Semiconductor Research Corporation (SRC) and the Defense Advanced Projects Research Agency (DARPA).
Biography
Naresh R. Shanbhag received his doctorate from the University of Minnesota (1993) in Electrical Engineering. From 1993 to 1995, he worked at AT&T Bell Laboratories at Murray Hill where he was the lead chip architect for AT&T’s 51.84 Mb/s transceiver chips over twisted-pair wiring for Asynchronous Transfer Mode (ATM)-LAN and very high-speed digital subscriber line (VDSL) chip-sets. Since August 1995, he is with the Department of Electrical and Computer Engineering, and the Coordinated Science Laboratory at the University of Illinois at Urbana-Champaign, where he is presently a Jack Kilby Professor of Electrical and Computer Engineering. His research interests are in the design of robust and energy-efficient integrated circuits and systems for communications including VLSI architectures for error-control coding, and equalization, noise-tolerant integrated circuit design, error-resilient architectures and systems, and system-assisted mixed-signal design. He has more than 200 publications in this area and holds twelve US patents. He is also a co-author of the research monograph Pipelined Adaptive Digital Filters published by Kluwer Academic Publishers in 1994.
Dr. Shanbhag received the 2010 Richard Newton GSRC Industrial Impact Award, became an IEEE Fellow in 2006, received the 2006 IEEE Journal of Solid-State Circuits Best Paper Award, the 2001 IEEE Transactions on VLSI Best Paper Award, the 1999 IEEE Leon K. Kirchmayer Best Paper Award, the 1999 Xerox Faculty Award, the Distinguished Lecturership from the IEEE Circuits and Systems Society in 1997, the National Science Foundation CAREER Award in 1996, and the 1994 Darlington Best Paper Award from the IEEE Circuits and Systems Society.
Dr. Shanbhag served as an Associate Editor for the IEEE Transaction on Circuits and Systems: Part II (97-99) and the IEEE Transactions on VLSI (99-02 and 09-11), respectively. He is the General Chair of the 2013 IEEE Workshop on Signal Processing Systems, was the General co-Chair of the 2012 IEEE International Symposium on Low-Power Design (ISLPED), was the Technical Program co-Chair of the 2010 ISLPED, and served on the technical program (wireline subcommittee) committee of the International Solid-State Circuits Conference (ISSCC) from 2007-11. Dr. Shanbhag lead the Alternative Computational Models in the Post-Si Era research theme, in the DOD and Semiconductor Research Corporation (SRC) sponsored Microelectronics Advanced Research Corporation (MARCO) center under their Focus Center Research Program (FCRP) from 2006-12. Since January 2013, he is the founding Director of the Systems On Nanoscale Information fabriCs (SONIC) Center, a 5-year multi-university center funded by DARPA and SRC under the STARnet phase of FCRP to explore novel computing paradigms for the nanoscale era.
In 2000, Dr. Shanbhag co-founded and served as the Chief Technology Officer of Intersymbol Communications, Inc., a venture-funded fabless semiconductor start-up that provides DSP-enhanced mixed-signal ICs for electronic dispersion compensation of OC-192 optical links. In 2007, Intersymbol Communications, Inc., was acquired by Finisar Corporation, Inc.