Phillipe Flatresse
Program Manager for Fully Depleted SOI Technology
STMicroelectronics
Abstract
UTBB FD-SOI technology for Extreme Power Efficient SOCs
UTBB FD-SOI has become a must for modern mobile and consumer multimedia products targeting high performance at low power in a cost effective manner. This breakthrough technology brings a significant improvement in terms of performance and power saving, complemented by an excellent responsiveness to power management design techniques for energy efficiency optimization. Today, UTBB FD-SOI appears as the most compelling solution with respect to any process available on the market thanks to its ability to extend the life of 2D planar process and design architectures at low manufacturing risk.
This short course addresses the major challenges of designing power efficient SOCs in UTBB FD-SOI technology. A special focus is made on the unique boosters offered by this technology, in particular the body biasing techniques that offers a real differentiation in terms of design flexibility and enables best in class energy efficient SOCs.
Biography
Philippe Flatresse received M.S. degree in Electrical Engineering in 1995 and PhD degree in Microelectronics in 1999 from Grenoble institute of technology. During his thesis, he has developed the LETISOI spice model dedicated to SOI technologies at CEA LETI, the R&D laboratory from French Atomic Energy Commission.
In year 2000, he joined STMicroelectronics Central R&D to deploy the SOI digital design within the company. He has developed the first SOI standard cells and SRAM libraries as well as IOs including innovative ESD solutions. He has also invented several dedicated CAD tools and low power digital design techniques such as power switches. Thanks to this work, he has pioneered the SOI technology and demonstrated its key advantages for low power high performance digital applications. As design architect, his current research interests are the convergence of high performance and low standby power towards multimedia mobile applications thru disruptive digital and analog aware design solutions like dual gate power switches or extreme body bias techniques based on fully depleted SOI technology.
His expertise covers both bulk and SOI technologies, including electrical characterization, spice modeling, design of libraries, low power and high performance digital design techniques. He has authored or co-authored more than 50 technical papers in advanced CMOS technologies.